Browsing by Autor "C.-T.D. Lo"

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Advanced Mechanical Analysis Workflow for Chiplets Integration Predictive Design
(International Microelectronics Assembly and Packaging Society, 2025) Lan Cao; Chenyuan Kou; Chen-Chao Wang; C.-T.D. Lo
Chiplet-based designs offer a compelling value proposition compared to traditional monolithic System on Chip (SoC) architectures with advantages in IP reuse, performance, cost, and time to market. Mechanical modeling and analysis (M&A) play a critical role in enabling the integration of chiplets, spanning the chip-package-board-system domains to support product development. The integration of chiplets from various suppliers and deverse technologies introduces differences in material properties, thermal coefficients, and mechanical behaviors that presents a significant challenge in ensuring a good mechanical reliability across the chiplet-based integration system. Consequently, chiplet-based designs encounter more challenges to address the elevated mechanical stress and reliability concerns. Traditional mechanical analysis and simulation workflows are primarily tailored for monolithic SoC-based designs and are not readily applicable to chiplet-based designs. The latter can no longer afford to overlook issues related to mechanical and thermal stress induced by multiple chiplets, especially with the use of advanced 2.5D and high-density fanout packages. In this paper, an advanced mechanical analysis workflow for chiplet-based designs is proposed. The representative examples that demonstrate the efficacy of this workflow are also presented. The advanced mechanical analysis workflow involves modeling of chiplets interactions at the early design stage spanning from the Si level to package level and encompassing scales from micrometers to millimeters that includes the components such as Through-Silicon Vias (TSVs), HIgh Density Fanout Cu RDL (Redistribution Layer) and microbumps. Furthermore, the predictive mechanical analysis workflow extends to analyses at the millimeter to meter scale, considering entire systems and incorporating elements like heat sinks and printed circuit boards (PCBs). It represents a multifaceted process spanning chip-to-package co-design, stress analysis, thermal analysis, failure analysis, and chiplet-based design optimization.