James Brian RomaineThomas AshleyMario Pereira Martín2026-03-222026-03-22202210.1109/access.2022.3187439https://doi.org/10.1109/access.2022.3187439https://andeanlibrary.org/handle/123456789/52817Citaciones: 2This article introduces a new multiplier-less 32-bit fixed point architecture for estimating complex non-linear functions based on adapted shift only series expansions. This novel hardware structure has been proposed for use as a dedicated core unit in implantable medical devices. Its implementation in FPGA produces a mean squared error of 0.23% over the functions <i>sin</i>(<i>x</i>),<i>cos</i>(<i>x</i>),<i>e^ix</i> and <i>tan</i>^-1(<i>x</i>) when compared to unrestricted CPU implementations. These results are achieved with the use of only 133 sliced registers and 399 Look-up-tables (LUTs). Furthermore, the hardware performs extremely well in our hardware-in-the-loop real use case application for the detection of epilepsy by correctly detecting true positive seizures. When implemented into 130 nm technology via <i>GOOGLE Sky130 PDK</i> and <i>Openlane</i> EDA tools, the ASIC occupies a space of 0.0625 mm² which represents a 47% reduction when compared to competitors. In addition, its power consumption is reduced to 6.46 mW at 100 MHz <i>f_o</i> and just 0.4 &#x03BC;W at 1KHz <i>f_o</i>.enComputer scienceLookup tablePower consumptionFixed-point arithmeticFixed pointField-programmable gate arrayComputer hardwareApplication-specific integrated circuitMultiplier (economics)Reduction (mathematics)article