Kothakonda Durga BhavaniR. SireeshaK. RajuGanesh Kumar MarathulaRatalaKoteswara NaikSanam Nagedram2026-03-222026-03-22202110.1088/1742-6596/1804/1/012162https://doi.org/10.1088/1742-6596/1804/1/012162https://andeanlibrary.org/handle/123456789/59163Citaciones: 1Abstract In the present generation of VLSI domain, designing a circuit with less power, area, and delay has become challenge for every designer. In this article we have design and implemented a design for 5:2 compressor which is the vital component in CMOS multiplier circuits. The proposed compressor circuit design requires less transistor count i.e. 58 transistors. The Simulation results of proposed 5:2 compressor has substantially expanded the performance of power delay in contrast to earlier designs.enGas compressorMultiplier (economics)Transistor countVery-large-scale integrationCMOSTransistorComputer scienceElectronic engineeringElectronic circuitPower (physics)article