A 3D Convolution Accelerator Implemented on FPGA Using SDSoC
| dc.contributor.author | Jhon Ordoñez | |
| dc.contributor.author | Guillermo Sahonero-Alvarez | |
| dc.coverage.spatial | Bolivia | |
| dc.date.accessioned | 2026-03-22T15:27:27Z | |
| dc.date.available | 2026-03-22T15:27:27Z | |
| dc.date.issued | 2019 | |
| dc.description | Citaciones: 3 | |
| dc.description.abstract | Convolutional Neural Networks (CNNs) have become a popular and useful deep learning algorithm. However, the requirements of computation have also increased. As implementation of CNNs in Embedded Systems or Cyber-Physical Systems (CPS) is required, the need of efficient technologies of computation like FPGAs arise substantially. In this paper, we present a 3D convolution accelerator implemented on a Xilinx ZCU102 FPGA board. It achieves 32.08 GOP/s of performance and an efficiency of 3.58 GOP/s per Watt. This accelerator has been developed in Xilinx SDSoC environment. | |
| dc.identifier.doi | 10.1109/iestec46403.2019.00126 | |
| dc.identifier.uri | https://doi.org/10.1109/iestec46403.2019.00126 | |
| dc.identifier.uri | https://andeanlibrary.org/handle/123456789/52479 | |
| dc.language.iso | en | |
| dc.relation.ispartof | 2019 7th International Engineering, Sciences and Technology Conference (IESTEC) | |
| dc.source | Universidad Católica Bolivia San Pablo | |
| dc.subject | Field-programmable gate array | |
| dc.subject | Computer science | |
| dc.subject | Convolution (computer science) | |
| dc.subject | Computation | |
| dc.subject | Convolutional neural network | |
| dc.subject | Embedded system | |
| dc.subject | Hardware acceleration | |
| dc.subject | Deep learning | |
| dc.subject | Computer hardware | |
| dc.subject | Artificial neural network | |
| dc.title | A 3D Convolution Accelerator Implemented on FPGA Using SDSoC | |
| dc.type | article |